1. Field of the Invention
The present invention relates to a digital-to-analog (DA) converter for converting digital signals into analog signals, an analog-to-digital (AD) converter including this DA converter, and a semiconductor device, such as an imaging device. More particularly, the invention relates to a DA conversion mechanism using a current source cell matrix including an array-structured current source cells.
2. Description of the Related Art
Various DA converters for converting digital signals into analog signals are used in electronic apparatuses.
Physical-quantity-distribution detecting semiconductor devices including a plurality of unit elements (for example, pixels) which are disposed in a line or a matrix and which are responsive to electromagnetic waves, such as light or radiation, input from an external source are used in various fields.
For example, in the field of video equipment, charge-coupled device (CCD), metal oxide semiconductor (MOS), or complementary metal-oxide semiconductor (CMOS)-type solid-state imaging devices for detecting light, which is one example of physical quantities, are used. Such imaging devices read a physical quantity distribution obtained by converting light into an electric signal by using the unit elements (pixels in the solid-state imaging apparatuses). In the solid-state imaging devices, “solid-state” means that the imaging devices are formed of semiconductor.
One type of solid-state imaging device is an amplifying solid-state imaging device including active pixel sensors (APS), which are also referred to as “gain cells”, each active pixel sensor using an amplifying transistor in an image signal generator for generating pixel signals in accordance with signal charge generated by a charge generator. Many CMOS-type solid-state imaging devices have this type of structure.
In such an amplifying solid-state imaging device, to read out pixel signals to the exterior from the imaging device, address control is performed on a pixel portion including a plurality of unit pixels so that pixel signals can be selected from the corresponding unit pixels. That is, the amplifying solid-state imaging device is one example of address-control solid-state imaging device.
For example, in an amplifying solid-state imaging device, which is one type of X-Y address solid-state imaging device including unit pixels disposed in a matrix, MOS active elements (MOS transistors) are used for forming the pixels so that the pixels have an amplifying function by themselves. That is, signal charge (photoelectrons) stored in photodiodes, which are photoelectric transducers, is amplified by the active elements and is read as image information.
In this type of X-Y address solid-state imaging device, many pixel transistors are disposed in a two-dimensional matrix to form a pixel portion. Signal charge corresponding to incident light is stored line by line or pixel by pixel, and current or voltage signals in accordance with the stored signal charge are sequentially read out from the individual pixels by addressing. In most of the MOS (including CMOS)-type solid-state imaging devices, unit pixels are accessed line by line and pixel signals in one line are read out from the pixel portion to the exterior. In some of the MOS (or CMOS)-type solid-state imaging devices, analog pixel signals read out from the pixel portion are converted into digital signals by an AD converter before being output to the exterior (see, for example, Japanese Unexamined Patent Application Publication Nos. 2000-152082 and 2002-232291).
As disclosed in the above-described publications, there are various methods for performing AD conversion in terms of the circuit scale, processing speed, and resolution. One of the AD conversion methods is so-called “single-slope-integrating or ramp-signal-comparison AD conversion method”. In this method, an analog unit signal is compared with a reference signal which varies monotonously and used for digital signal conversion, and simultaneously with this comparison operation, counting is started. Then, based on the count value when the comparison operation is finished, a digital signal is obtained. In this type of AD conversion method, a DA converter is sometimes used for generating the reference signal.
There are also various methods for performing DA conversion in terms of the circuit scale, processing speed, and resolution. In one of the DA conversion methods, many current source cells weighted with predetermined current values are used, and among those current source cells, predetermined current source cells are selected based on a multi-bit digital input signal, and then, constant current outputs of the selected current source cells are added to each other. As a result, an analog current output corresponding to a digital input signal can be obtained.
In this type of DA converter, various modes can be employed in selecting current source cells corresponding to a digital input signal. One mode is a decoding mode (see Japanese Unexamined Patent Application Publication No. 5-191290). In the decoding mode, many current source cells uniformly weighted with a predetermined current value are used, and a multi-bit digital input signal is decoded into a decimal number. Then, current source cells are selected in accordance with the decimal number. Another mode is a binary mode in which a plurality of current source cells for outputting currents weighted with two to the power of certain numbers (or 1/two-to-the-power-of-certain-numbers) are used, and current source cells in accordance with the bit value of a multi-bit digital input signal are selected. Another mode is a composite mode (see Japanese Unexamined Patent Application Publication No. 11-17545). In the composite mode, a multi-bit digital input signal is divided into higher bits and lower bits, and the decoding mode is applied to the higher bits and the binary mode is applied to the lower bit.
In the composite mode, in the case of the higher bits, many current source cells uniformly weighted with a predetermined current value are prepared, and then, the higher bits of the multi-bit digital input signal are decoded into a decimal number, and the decimal number is latched. Then, current source cells are selected in accordance with the decimal number. In the case of the lower bits, many current source cells uniformly weighted with 1/two-to-the-power-of-certain-numbers of the current value weighted for the current source cells corresponding to the higher bits are prepared, and then, the lower bits of the multi-bit digital input signal are latched. Then, current source cells are selected in accordance with the lower bits. Subsequently, by adding the output currents of the current source cells selected for the higher bits and the lower bits on the basis of the latched values, an analog current output corresponding to the digital input signal value can be obtained. For the decoding of the higher bits, full decoding is performed.